1. Field of the Invention
The present invention generally relates to multi-level output circuits, and more particularly, to a multi-level output circuit capable of selectively outputting signals of multiple levels.
2. Description of the Related Art
FIG. 1 is a circuit configuration diagram of an example of conventional three-level output circuits.
A conventional three-level output circuit 1 is constructed by a high-level output circuit 11, a middle-level output circuit 12, and a low-level output circuit 13.
The high-level output circuit 11 includes a reference voltage source 21, an operational amplifier 22, and a switch 23. The reference voltage source 21 generates a reference voltage Vref1 . The reference voltage Vref1 generated by the reference voltage source 21 is supplied to a noninverting input terminal of the operational amplifier 22.
The operational amplifier 22 forms a noninverting amplifier circuit. A drive voltage Vcc is supplied to the operational amplifier 22 via the switch 23. The switch 23 is connected to a control terminal Tc1. The switch 23 is turned ON when the voltage of the control terminal Tc1 is at a high level and turned OFF when the voltage of the control terminal Tc1 is at a low level.
The operational amplifier 22 is in an operating state while the switch 23 is turned ON and supplies the reference voltage Vref1 to an output terminal Tout. In addition, the operational amplifier 22 is in a non-operating state while the switch 23 is turned OFF and does not supply the reference voltage Vref1 to the output terminal Tout.
The middle-level output circuit 12 includes a reference voltage source 31, an operational amplifier 32, and a switch 33. The reference voltage source 31 generates a middle-level reference voltage Vref2 that is lower than the reference voltage Vref1. the reference voltage Vref2 generated by the reference voltage source 31 is supplied to a noninverting input terminal of the operational amplifier 32.
The operational amplifier 32 forms a noninverting amplifier circuit. The drive voltage Vcc is supplied to the operational amplifier 32 via the switch 33. The switch 33 is connected to a control terminal Tc2. The switch 33 is turned ON when the voltage of the control terminal Tc2 is at a high level and turned OFF when the voltage of the control terminal Tc2 is at a low level.
The operational amplifier 32 is in an operating state while the switch 33 is turned ON and supplies the reference voltage Vref2 to the output terminal Tout. In addition, the operational amplifier 32 is in a non-operating state while the switch 33 is turned OFF and does not supply the reference voltage Vref2 to the output terminal Tout.
The low-level output circuit 13 is constructed by a resistance R1. The resistance R1 is connected between the output terminal Tout and the ground. When the high-level output circuit 11 and the middle-level output circuit 12 are in the non-operating states, the low-level output circuit 13 connects the output terminal Tout to the ground so that the output terminal Tout is at a low level.
FIG. 2 is a timing diagram for explaining the operation of the example of conventional three-level output circuits. FIG. 2-A indicates the voltage waveform of the control terminal Tc1, FIG. 2-B indicates the voltage waveform of the control terminal Tc2, and FIG. 2-C indicates the voltage waveform of the output terminal Tout.
In a case where, during a term T1 (refer to FIG. 2), the voltage of the control terminal Tc1 is at a high level and the voltage of the control terminal Tc2 is at a low level, the switch 23 is turned ON and the switch 33 is turned OFF. When the switch 23 is turned ON, the drive voltage Vcc is applied to the operational amplifier 22, and the reference voltage Vref1 is supplied to the output terminal Tout. In addition, when the switch 33 is turned OFF, the drive voltage Vcc is not supplied to the operational amplifier 32. Consequently, the operational amplifier 32 takes the non-operating state. Hence, the output voltage Vref1 of the operational amplifier 22 is supplied to the output terminal Tout, and the voltage of the output terminal Tout becomes a high level as indicated by FIG. 2-C.
When, during a term T2 (refer to FIG. 2), the voltage of the control terminal Tc1 is at a low level and the voltage of the control terminal Tc2 is at a high level, the switch 23 is turned OFF and the switch 33 is turned ON. When the switch 23 is turned OFF, the drive voltage Vcc is not supplied to the operational amplifier 22. As a result, the operational amplifier 22 takes the non-operating state. Additionally, when the switch 33 is turned ON, the drive voltage Vcc is applied to the operational amplifier 32. Thus, the operational amplifier 32 takes the operating state. Hence, the output voltage Vref2 of the operational amplifier 32 is supplied to the output terminal Tout, and the voltage of the output terminal Tout becomes a middle level as indicated by FIG. 2-C.
When, during a term T3 (FIG. 2), when the voltages of the control terminals Tc1 and Tc2 are both at low levels, the switches 23 and 33 are both turned OFF. When the switch 23 is turned OFF, the drive voltage Vcc is not applied to the operational amplifier 22. Thus, the operational amplifier 22 takes the non-operating state. In addition, when the switch 33 is turned OFF, the drive voltage Vcc is not supplied to the operational amplifier 32. Consequently, the operational amplifier 32 takes the non-operating state. Hence, neither of the high-level output circuit 11 nor the middle-level output circuit 12 supplies voltage to the output terminal Tout. Accordingly, the output terminal Tout is connected to the ground via the resistance R1. Thus, the output terminal Tout is at a low level as indicated by FIG. 2-C.
As described above, the output level is selectively determined from among the three levels: the high, middle, and low levels.
In the conventional three-level output circuit, however, three circuits, that is, the high-level output circuit 11 for outputting a high level, the middle-level output circuit 12 for outputting a middle level, and the low-level output circuit 13 for outputting a low level, are required. Accordingly, there are problems in that the circuit configuration becomes complicated, for example.